Search AI news

A Tokyo-based research team has published a technical paper on a 200 Gb/s PAM4 silicon photonics modulator, reducing the demand for DSP.

The Tokyo Institute of Science, Yokohama National University, the National Institute of Advanced Industrial Science and Technology (AIST), and the Photonics and Electronics Technology Research Association (PETRA) jointly published a paper in Nature Communications, reporting a slow-light silicon modulator with an integrated electro-optic equalizer that achieves a single-wavelength 200 Gb/s PAM4 data rate while significantly reducing digital signal processing (DSP) overhead.

Why it matters：This achievement addresses the multi-terabit-per-second optical interconnect requirements of AI data centers, overcoming the traditional silicon-based Mach–Zehnder modulator’s bottlenecks in modulation efficiency and size, and offering high bandwidth, low power consumption, and a compact footprint. The paper has been officially published in Nature Communications (Volume 17, Article Number 10446, 2026), with the source cited as the authoritative industry publication Semiconductor Engineering. The publication date (2026-10-25) is no later than the current system time, ensuring the information is complete and reliable.

Amazon SageMaker launches the Training Session API: users can write custom training loops for large models without managing GPUs.

Amazon SageMaker has released the Training Sessions API, enabling users to implement custom large-model training workflows—such as SFT, RLHF, GRPO, and KTO—using pure Python scripts. GPU resource scheduling, fault tolerance, distributed execution, and checkpoint management are all handled by the service.

NVIDIA drives the transformation of Europe’s retail sector: Open models and physical intelligence are being implemented in e-commerce, warehousing, and virtual try-on.

European retailers are leveraging NVIDIA-accelerated open large models and physics‑AI technologies to achieve large‑scale deployment across scenarios such as digital product discovery, intelligent warehouse simulation, virtual try‑on, and accelerated R&D. Companies including Shopify, Zooplus, L’Oréal, and the Otto Group have used tools like the Nemotron series of models, Omniverse digital twins, and ALCHEMI molecular simulations to significantly reduce inference costs, improve search accuracy, shorten R&D cycles, and validate improvements in conversion rates and sales growth.

NVIDIA cuDSS officially released: Accelerating the solution of sparse linear systems in engineering and scientific simulations

On October 26, 2026 (UTC), NVIDIA announced that the cuDSS library has entered General Availability (GA). This CUDA-X library is specifically designed to efficiently solve large-scale sparse linear systems on GPUs, significantly boosting simulation throughput and iterative efficiency across fields such as chip design, aerospace, and industrial systems.

TorchNeuron System-Level Performance Analysis (Part 1): End-to-End Profiling Based on the AWS Trainium Chip

This article is the first in a series of technical blog posts jointly published by Hugging Face and Amazon, systematically introducing how to use TorchNeuron on AWS Trainium AI accelerator chips for PyTorch model inference performance analysis. It covers the principles of Neuron backend integration, methods for configuring torch.profiler, the use of NeuronConfig and NeuronProfiler tools, and visualized tracing with Neuron Explorer. Additionally, using RMSNorm as an example, it compares the device‑time differences among three implementations: plain PyTorch, the built-in torch.rms_norm fusion, and torch.compile’s automatic fusion.

i14 releases the Laplace 3B linear attention model: inference with fixed-state memory, implemented on AWS Trainium2 and native PyTorch.

i14 has launched the Laplace 3B model with 3.028 billion parameters, which replaces Softmax attention with Gated Linear Attention (GLA). During inference, its per-sequence recursive state remains constant at 29.5 MB, independent of context length. The model was trained and validated on a single AWS trn2.48xlarge instance (equipped with 16 Trainium 2 chips), achieving a training throughput of 120,000 tokens per second and an inference throughput of 11,544 output tokens per second (with 1,280 concurrent sequences). All performance metrics are based on internal measurements conducted by i14 and the AWS GenAIIC team.